In an SMP (symmetric multiprocessing) computer system with high-level packaging, it is often necessary to allow latencies on cards, wires, or boards that exceed the cycle times of the transferred data. In order to allow these transfers to take place, source-synchronous pipelined interfaces have been used in the s/390 machines of IBM. This allows for the proper capturing of the data within a small window, or ‘eye’.
In order to capture this data, there is usually a calibration or learning period. A known data pattern is sent across the interface and the receiver compensates for the various package tolerances using calibration techniques.
However, over time, these large-latency interfaces can drift due to environmental changes like voltage, temperature, end-of-life degradation, etc.
The prior s/390 IBM machines only handled the first calibration. There was no way to re-calibrate an interface once it was up and running. Therefore, the cumulative degradations could eventually cause a system failure.
Also, in a test environment, we often apply environmental stress to a machine as well as frequency changes. We often want to run a hardware/architecture exerciser (like SAK or PCX) under several environments (about 16 voltage corners as well as cycling up or down the frequency), the interface often fails without a re-calibration. If the system is not recalibrated under the new environment, the system must be restarted for every test. Therefore, our test time is jeopardized.